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Just thought I'd share the latest contribution from an engineer.
(English is not his mother tongue.) I have corrected the
" The bus status T1 is not always associated with a T1 on
the external bus. In some cases, the bus status may
precede the external T1. During word accesses to 8-bit
wide Expansion Memory, the first Expansion Memory bus
cycle is flagged as a core bus T1 and the second bus
cycle is not a core bus T1. "
The bus status signals reflect activity on the core
bus. Therefore, when a word is accessed in 8-bit
Expansion Memory, these signals do not accurately
reflect the status of the external bus. In this case,
the word is broken into two bytes, and two cycles are
required for the operation. The first Expansion Memory
cycle is flagged as a T1 cycle of the core bus. The
second is not a core bus cycle, and the bus status
signals will be 00.
I know, it's passive. I save my energy for more important